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TC7116 TC7116A TC7117 TC7117A 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
FEATURES
s Low Temperature Drift Internal Reference TC7116/TC7117 ............................. 80 ppm/C Typ TC7116A/TC7117A ........................ 20 ppm/C Typ s Display Hold Function s Directly Drives LCD or LED Display s Guaranteed Zero Reading With Zero Input s Low Noise for Stable Display ......... 2V or 200 mV Full-Scale Range (FSR) s Auto-Zero Cycle Eliminates Need for Zero Adjustment Potentiometer s True Polarity Indication for Precision Null Applications s Convenient 9V Battery Operation (TC7116/TC7116A) s High Impedance CMOS Differential Inputs .... 1012 s Low Power Operation .................................... 10 mW
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GENERAL DESCRIPTION
The TC7116A/TC7117A are 3-1/2 digit CMOS analogto-digital converters (ADCs) containing all the active components necessary to construct a 0.05% resolution measurement system. Seven-segment decoders, polarity and digit drivers, voltage reference, and clock circuit are integrated on-chip. The TC7116A drives liquid crystal displays (LCDs) and includes a backplane driver. The TC7117A drives common anode light emitting diode (LED) displays directly with an 8-mA drive current per segment. These devices incorporate a display hold (HLDR) function. The displayed reading remains indefinitely, as long as HLDR is held high. Conversions continue, but output data display latches are not updated. The reference - low input (VREF) is not available as it is with the TC7106/ - 7107. VREF is tied internally to analog common in the TC7116A/7117A devices. The TC7116A/7117A reduces linearity error to less than 1 count. Roll-over error (the difference in readings for equal magnitude but opposite polarity input signals) is below 1 count. High-impedance differential inputs offer 1 pA leakage current and a 1012 input impedance. The 15 VP-P noise performance guarantees a "rock solid" reading. The auto-zero cycle guarantees a zero display reading with a 0V input. The TC7116A and TC7117A feature a precision, lowdrift internal reference, and are functionally identical to the TC7116/TC7117. A low-drift external reference is not normally required with the TC7116A/TC7117A.
0.1 F 34 1 M + ANALOG 0.01 F INPUT - + C REF 31 + V IN - 30 V IN 32 ANALOG COMMON LCD DISPLAY (TC7116/7116A) 33 1 OR COMMON ANODE LED DISPLAY (TC7117/7117A) - C REF HLDR 2-19 SEGMENT 22-25 DRIVE POL 20 BP/GND 21 V+ 35 24 k + 36 VREF 100 mV 1 k 9V MINUS SIGN BACKPLANE DRIVE DISPLAY HOLD
2 3 4 5 6 7
ORDERING INFORMATION PART CODE TC711X X X XXX
6 = LCD 7 = LED
}
A or blank* R (reversed pins) or blank (CPL pkg. only) * "A" parts have an improved reference TC Package Code (see below): Package Code
CKW CLW CPL IJL
Package
44-Pin PQFP 44-Pin PLCC 40-Pin Plastic DIP 40-Pin CerDIP
Temperature Range
0C to +70C 0C to +70C 0C to +70C - 25C to +85C
AVAILABLE PACKAGES
40-Pin Plastic DIP 40-Pin CerDIP
47 k
TC7116/A 28 V BUFF TC7117/A 0.47 F 29 0.22 F 27 CAZ + VREF
44-Pin Plastic Quad Flat Package Formed Leads
V - 26 VINT OSC2 OSC3 OSC1 39 38 COSC 40 R OSC 100 pF 100 k
TO ANALOG COMMON (PIN 32)
3 CONVERSIONS/SEC
44-Pin Plastic Chip Carrier PLCC
Figure 1. Typical TC7116/A/7/A Operating Circuit
TC7116/A/7117/A-7 10/18/96
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TC7116 TC7116A TC7117 TC7117A
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage TC7116/TC7116A: V+ to V- ................................. 15V TC7117/TC7117A: V+ to GND ............................. +6V V- to GND ............................- 9V Analog Input Voltage (Either Input) (Note 1) ........ V+ to V- Reference Input Voltage (Either Input) ................. V+ to V- Clock Input TC7116/TC7116A ..................................... TEST to V+ TC7117/TC7117A ...................................... GND to V+ Package Power Dissipation, TA 70C (Note 2) CerDIP ..............................................................2.29W Plastic DIP ........................................................1.23W Plastic Chip Carrier (PLCC) ..............................1.23W Plastic Quad Flat Package (PQFP) ..................1.00W
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
Operating Temperature "C" Device .............................................. 0C to +70C "I" Device .......................................... - 25C to +85C Storage Temperature ............................ - 65C to +150C Lead Temperature (Soldering, 10 sec) ................. +300C
*Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (Note 3)
Parameter
Zero Input Reading Ratiometric Reading Roll-Over Error (Difference in Reading for Equal Positive and Negative Readings Near Full Scale) Linearity (Maximum Deviation From Best Straight Line Fit) Common-Mode Rejection Ratio (Note 4) Noise (Peak-to-Peak Value Not Exceeded 95% of Time) Leakage Current at Input Zero Reading Drift
Test Conditions
VIN = 0V Full Scale = 200 mV VIN = VREF VREF = 100 mV -VIN = +VIN 200 mV or 2V
Min
-- 999 -1
Typ
0 999/1000 0.2
Max
-- 1000 +1
Unit
Digital Reading Digital Reading Counts
Full Scale = 200 mV or 2V VCM = 1V, VIN = 0V Full Scale = 200 mV VIN = 0V Full Scale = 200 mV VIN = 0V VIN = 0V "C" Device: 0C to +70C "I" Device: -25C to +85C VIN = 199 mV "C" Device: 0C to +70C (Ext Ref = 0 ppm/C) "I" Device: -25C to +85C Note 6 TC7116/A Only TC7117/A Only Both VIN = 0V 25 k Between Common and Positive Supply "C" Device: 0C to +70C TC7116A/TC7117A TC7116/TC7117
-1 -- -- -- -- -- -- -- 30 -- -- + - 1.5 V -- 2.4
0.2 50 15 1 0.2 1 1 -- 70 -- -- -- 0.8 3.05
+1 -- -- 10 1 2 5 20 -- Test +1.5 GND +1.5 -- 1.8 3.35
Counts V/V V pA V/C v/C ppm/C ppm/C k V V V mA V
Scale Factor Temperature Coefficient
Input Resistance, Pin 1 VIL , Pin 1 VIL , Pin 1 VIH, Pin 1 Supply Current (Does Not Include LED Current for 7117/A) Analog Common Voltage (With Respect to Positive Supply) Temperature Coefficient of Analog Common (With Respect to Positive Supply)
-- --
20 80
50 --
ppm/C ppm/C
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3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
TC7116 TC7116A TC7117 TC7117A
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ELECTRICAL CHARACTERISTICS (Cont.)
Parameter
Temperature Coefficient of Analog Common (With Respect to Positive Supply) TC7116/TC7116A ONLY Peak-to-Peak Segment Drive Voltage TC7116/TC7116A ONLY Peak-to-Peak Backplane Drive Voltage TC7117/TC7117A ONLY Segment Sinking Current (Except Pin 19) TC7117/TC7117A ONLY Segment Sinking Current (Pin 19 Only)
Test Conditions
"I" Device: -25C to +85C 25 k Between Common and Positive Supply (TC7116A/TC7117A) V+ to V- = 9V (Note 5) V+ to V- = 9V (Note 5) V+ = 5V Segment Voltage = 3V V+ = 5V Segment Voltage = 3V
Min
--
Typ
--
Max
75
Unit
ppm/C
2 3 4 5 6 7
4 4 5 10
5 5 8 16
6 6 -- --
V V mA mA
NOTES: 1. Input voltages may exceed supply voltages, provided input current is limited to 100 A. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. Unless otherwise noted, specifications apply at TA = +25C, fCLOCK = 48 kHz. TC7116/TC7116A and TC7117/TC7117A are tested in the circuit of Figure 1. 4. Refer to "Differential Input" discussion. 5. Backplane drive is in-phase with segment drive for "OFF" segment, 180 out-of-phase for "ON" segment. Frequency is 20 times conversion rate. Average DC component is less than 50 mV. 6. The TC7116/TC7116A logic inputs have an internal pull-down resistor connected from HLDR, pin 1 to TEST, pin 37. The TC7117/TC7117A logic inputs have an internal pull-down resistor connected from HLDR, pin 1 to GND, pin 21.
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TC7116 TC7116A TC7117 TC7117A
PIN CONFIGURATIONS
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
HLDR D1 C1 B1 1's A1 F1 G1 E1 D2
1 2 3 4 5 6 7 8 9 TC7116IPL TC7116AIPL TC7117CPL TC7117ACPL (PDIP)
40 OSC 1 39 OSC 2
HLDR D1 C1 B1 1's A1 F1 G1 E1 D2
1 2 3 4 5 6 7 8 9 TC7116IJL TC7116AIJL TC7117IJL TC7117AIJL (CerDIP)
40 OSC 1 39 OSC 2
38 OSC 3 37 TEST + 36 V REF 35 V+ + 34 CREF - 33 CREF 32 COMMON + 31 V IN - 30 V IN 29 CAZ 28 VBUFF 27 V INT 26 V - 25 G 2 24 C 3 23 A 3 22 G 3 100's 100's 1000's
38 OSC 3 37 TEST + 36 V REF 35 V+ + 34 CREF - CREF 33 32 COMMON + 31 V IN - 30 V IN 29 CAZ 28 VBUFF 27 V INT 26 V - 25 G 2 24 C 3 23 A 3 22 G 3 21 BP/GND (TC7116/7117) (TC7116A/TC7117A)
COMMON
C2 10 10's B2 11 A2 12 F2 13 E 2 14 D3 15 100's B3 16 F3 17 E 3 18 1000's AB 4 19 POL 20 (MINUS SIGN)
C2 10 10's B2 11 A2 12 F2 13 E 2 14 D3 15 B3 16 F3 17 E 3 18 AB 4 19 POL 20 (MINUS SIGN)
100's
21 BP/GND (TC7116/7117) (TC7116A/TC7117A)
HLDR
REF HI
OSC 1
OSC 2
OSC 3
REF HI + V + C REF - C REF
IN LO
TEST
IN HI
BUFF
A/Z
INT
35
NC
A1
B1
C1
D1
6
5
4
3
2
1
44
43
42
41
40
44 43
42
41 40 39
38
37
36
F1 7 G1 8 E1 9
D2 10
39 V
+
V-
34
NC 1 NC 2 TEST 3
OSC 3 4
33 NC 32 G
+ 38 CREF - 37 CREF
36 COMMON
2
31 C 3 30 A 3
C2 11
NC 12
B2 13
A 2 14 F 2 15 E 2 16
TC7116CLW TC7116ACLW TC7117CLW TC7117ACLW (PLCC)
35 IN HI 34 NC 33 IN LO 32 A/Z 31 BUFF 30 INT 29 V -
NC 5
OSC 2 6 OSC 1 7
TC7116CKW TC7116ACKW TC7117CKW TC7117ACKW (FLAT PACKAGE)
29 G 3 28 BP/
GND
27 POL 26 AB 4 25 E3 24 F3 23 B3
HLDR 8 D1 9 C 1 10 B 1 11
12 13 14
D 3 17
18 19 20 21 22 23 24 25 26 27 28
15 16
17
18
19
20
21 22
4
G3
A3
C3
POL
NC BP/ GND
G2
B3
D2
C2
B2
A2
A1
G1
NOTES: 1. NC = No internal connection. + 2. Pins 9, 25, 40, and 56 are connected to the die substrate. The potential at these pins is approximately V . No external connections should be made.
AB
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E1
E2
D3
F3
E3
F1
F2
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
TC7116 TC7116A TC7117 TC7117A
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PIN DESCRIPTION
40-Pin PDIP/ 40-PinCerDIP Pin Number Normal
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
44-Pin Plastic Quad Flat Package Pin Number
8 9 10 11 12 13 14 15 9 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35
2
Symbol
HLDR D1 C1 B1 A1 F1 G1 E1 16 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP GND G3 A3 C3 G2 V- VINT
Description
Hold pin, Logic 1 holds present display reading. Activates the D section of the units display. Activates the C section of the units display. Activates the B section of the units display. Activates the A section of the units display. Activates the F section of the units display. Activates the G section of the units display. Activates the E section of the units display. D2 Activates the D section of the tens display. Activates the C section of the tens display. Activates the B section of the tens display. Activates the A section of the tens display. Activates the F section of the tens display. Activates the E section of the tens display. Activates the D section of the hundreds display. Activates the B section of the hundreds display. Activates the F section of the hundreds display. Activates the E section of the hundreds display. Activates both halves of the 1 in the thousands display. Activates the negative polarity display. LCD backplane drive output (TC7116/TC7116A). Digital ground (TC7117/TC7117A). Activates the G section of the hundreds display. Activates the A section of the hundreds display. Activates the C section of the hundreds display. Activates the G section of the tens display. Negative power supply voltage. Integrator output. Connection point for integration capacitor. See Integration Capacitor section for additional details. Integration resistor connection. Use a 47 k resis tor for 200 mV full-scale range and a 470 k resistor for 2V full-scale range. The size of the auto-zero capacitor influences system noise. Use a 0.47 F capacitor for 200 mV full scale and a 0.047 F capacitor for 2V full scale. See Auto-Zero Capacitor paragraph for more details. The analog LOW input is connected to this pin. The analog HIGH input is connected to this pin. This pin is primarily used to set the analog commonmode COMMON voltage for battery operation or in systems where the input signal is referenced to the power supply. See Analog Common paragraph for more details. It also acts as a reference voltage source.
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3 4 5 6 7
28
36
VBUFF
29
37
CAZ
30 31 39
38 39 40
- VIN + V IN COMMON
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TC7116 TC7116A TC7117 TC7117A
PIN DESCRIPTION (Cont.)
40-Pin CerDIP 40-Pin PDIP Pin Number Normal
33 34
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
44-Pin Plastic Quad Flat Package Pin Number
41 42
Symbol
C- REF C+ REF
Description
See pin 34. A 0.1 F capacitor is used in most applications. If a - large, common-mode voltage exists (e.g., the VIN pin is not at analog common), and a 200 mV scale is used, a 1 F capacitor is recommended and will hold the roll-over error to 0.5 count. Positive power supply voltage. The analog input required to generate a full-scale output (1999 counts). Place 100 mV between pins 32 and 36 for 199.9 mV full scale. Place 1V between pins 32 and 36 for 2V full scale. See paragraph on Reference Voltage. Lamp test. When pulled HIGH (to V+), all segments will be turned on and the display should read -1888. It may also be used as a negative supply for externallygenerated decimal points. See Test paragraph for more details. See pin 40. See pin 40. Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings per sec), connect pin 40 to the junction of a 100 k resistor and a 100 pF capacitor. The 100 k resistor is tied to pin 39 and the 100 pF capacitor is tied to pin 38.
35 36
43 44
V+ V+ REF
37
3
TEST
38 39 40
4 6 7
OSC3 OSC2 OSC1
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TC7116 TC7116A TC7117 TC7117A
CAZ + 35 AUTOZERO 29 INTEGRATOR LOW TEMP DRIFT - + + TO DIGITAL SECTION COMPARATOR
1
+ C REF V + 34
+ VREF
CREF - C REF 33 - V BUFF
RINT V 28
CINT VINT 27
2 3 4 5 6 7
36
10 A + V IN 31 INT A/Z
A/Z + DE (-)
DE (+) A/Z - +
ZENER VREF
ANALOG COMMON - V IN
32
DE (+)
DE (-) + V -3V TC7116 TC7116A TC7117 TC7117A
30 INT
A/Z & DE () 26 V-
Figure 3. Analog Section of TC7116/TC7116A and TC7117/TC7117A
ANALOG SECTION (All Pin designations refers to 40-Pin Dip)
Figure 3 shows the block diagram of the analog section for the TC7116/TC7116A and TC7117/TC7117A. Each measurement cycle is divided into three phases: (1) autozero (A-Z), (2) signal integrate (INT), and (3) reference integrate (REF) or deintegrate (DE).
Reference Integrate Phase
The final phase is reference integrate, or deintegrate. Input low is internally connected to analog common and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. The digital reading displayed is: 1000 x VIN . VREF
Auto-Zero Phase
High and low inputs are disconnected from the pins and internally shorted to analog common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the system to charge the auto-zero capacitor (CAZ) to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, A-Z accuracy is limited only by system noise. The offset referred to the input is less than 10 V.
Reference
The positive reference voltage (V+ ) is referred to REF analog common.
Differential Input
This input can accept differential voltages anywhere within the common-mode range of the input amplifier or, specifically, from 1V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86 dB, typical. However, since the integrator also swings with the common-mode voltage, care must be exercised to ensure that the integrator output does not saturate. A worst- case condition would be a large, positive commonmode voltage with a near full-scale negative differential input voltage. The negative-input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. For these critical applications, the integrator swing can be reduced to less than the
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Signal-Integrate Phase
The auto-zero loop is opened, the internal short is removed, and the internal high and low inputs are connected to the external pins. The converter then integrates the differential voltages between V+IN and V - for a fixed IN time. This differential voltage can be within a wide common-mode range; 1V of either supply. However, if the input signal has no return with respect to the converter power supply, V - can be tied to analog common to establish the IN correct common-mode voltage. At the end of this phase, the polarity of the integrated signal is determined. TELCOM SEMICONDUCTOR, INC.
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TC7116 TC7116A TC7117 TC7117A
V+
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
V+
V+ 6.8 k TC7116 TC7116A TC7117 TC7117A V+ REF COMMON
V+ 4049
TC7116 TC7116A
20 k
BP
TC9491CZM 1.2V REF
21 GND 37
TO LCD DECIMAL POINT TO LCD BACKPLANE
TEST
Figure 5. Simple Inverter for Fixed Decimal Point Figure 4. Using an External Reference V+
recommended 2V full-scale swing with little loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity.
V+ BP TO LCD DECIMAL POINTS
Analog Common
This pin is included primarily to set the common-mode voltage for battery operation (TC7116/TC7116A) or for any system where the input signals are floating with respect to the power supply. The analog common pin sets a voltage approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog common has some attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the analog common voltage will have a low voltage coefficient (0.001%/ %), low output impedance (15), and a temperature coefficient of less than 20 ppm/C, typically, and 50 ppm maximum. The TC7116/TC7117 temperature coefficients are typically 80 ppm/C. An external reference may be used, if necessary, as shown in Figure 4. - Analog common is also used as V IN return during auto- zero and deintegrate. If VIN is different from analog common, a common-mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in - some applications, VIN will be set at a fixed, known voltage (power supply common for instance). In this application, analog common should be tied to the same point, thus removing the common-mode voltage from the converter. The same holds true for the reference voltage; if it can be conveniently referenced to analog common, it should be. This removes the common-mode voltage from the reference system. Within the IC, analog common is tied to an N-channel FET that can sink 30 mA or more of current to hold the voltage 3V below the positive supply (when a load is trying
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TC7116 TC7116A
DECIMAL POINT SELECT
4030 TEST GND
Figure 6. Exclusive "OR" Gate for Decimal Point Drive
TC7116/TC7116A TC7117/TC7117A
40 CRYSTAL EXT OSC
39
TO COUNTER 38
RC NETWORK TO TEST PIN ON TC7116/TC7116A TO GROUND PIN ON TC7117/TC7117A
Figure 7. Clock Circuits
to pull the analog common line positive). However, there is only 10 A of source current, so analog common may easily be tied to a more negative voltage, thus overriding the internal reference.
TEST
The TEST pin serves two functions. On the TC7117/ TC7117A, it is coupled to the internally-generated digital supply through a 500 resistor. Thus, it can be used as a TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
TC7116 TC7116A TC7117 TC7117A
voltage is switched. The BP frequency is the clock frequency 800. For 3 readings per second, this is a 60-Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude, and are in-phase with BP when OFF, but out-of-phase when ON. In all cases, negligible DC voltage exists across the segments. Figure 9 is the digital section of the TC7117/TC7117A. It is identical to the TC7116/TC7116A, except that the regulated supply and BP drive have been eliminated, and the segment drive is typically 8 mA. The 1000's output (pin 19) sinks current from two LED segments, and has a 16-mA drive capability. The TC7117/TC7117A are designed to drive common anode LED displays. In both devices, the polarity indication is ON for analog inputs. If V - and V + are reversed, this indication can be IN IN reversed also, if desired.
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negative supply for externally-generated segment drivers, such as decimal points or any other presentation the user may want to include on the LCD. (Figures 5 and 6 show such an application.) No more than a 1 mA load should be applied. The second function is a "lamp test." When TEST is pulled HIGH (to V+), all segments will be turned ON and the display should read -1888. The TEST pin will sink about 10 mA under these conditions.
2 3 4
DIGITAL SECTION
Figures 8 and 9 show the digital section for TC7116/ TC7116A and TC7117/TC7117A, respectively. For the TC7116/TC7116A (Figure 8), an internal digital ground is generated from a 6V zener diode and a large P-channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the backplane (BP)
TC7116 TC7116A BACKPLANE 21
LCD PHASE DRIVER TYPICAL SEGMENT OUTPUT + V 0.5 mA SEGMENT OUTPUT 2 mA LATCH 7-SEGMENT DECODE 7-SEGMENT DECODE
5
7-SEGMENT DECODE / 200
INTERNAL DIGITAL GROUND THOUSANDS HUNDREDS TENS UNITS
6
35 70 k 6.2V 500 26 V- V +
TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK /4 LOGIC CONTROL VTH = 1V 40 OSC 1 39 OSC 2 38 OSC 3 INTERNAL DIGITAL GROUND 1 HLDR
37
TEST
7
Figure 8. TC7116/TC7116A Digital Section
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TC7116 TC7116A TC7117 TC7117A
System Timing
The clocking method used for the TC7116/TC7116A and TC7117/TC7117A is shown in Figure 9. Three clocking methods may be used: (1) An external oscillator connected to pin 40. (2) A crystal between pins 39 and 40. (3) An RC network using all three pins. The oscillator frequency is 4 before it clocks the decade counters. It is then further divided to form the three convert-cycle phases: signal integrate (1000 counts), reference deintegrate (0 to 2000 counts), and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference deintegrate. This makes a complete measure cycle of 4000 (16,000 clock pulses) independent of input voltage. For 3 readings per second, an oscillator frequency of 48 kHz would be used.
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
To achieve maximum rejection of 60-Hz pickup, the signal-integrate cycle should be a multiple of 60 Hz. Oscillator frequencies of 240 kHz, 120 kHz, 80 kHz, 60 kHz, 48 kHz, 40 kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200 kHz, 100 kHz, 66-2/3 kHz, 50 kHz, 40 kHz, etc. would be suitable. Note that 40 kHz (2.5 readings per second) will reject both 50 Hz and 60 Hz.
HOLD Reading Input
When HLDR is at a logic HIGH the latch will not be updated. Analog-to-digital conversions will continue but will not be updated until HLDR is returned to LOW. To continuously update the display, connect to test (TC7116/TC7116A) or ground (TC7117/TC7117A), or disconnect. This input is CMOS compatible with 70 k typical resistance to TEST (TC7116/TC7116A) or ground (TC7117/TC7117A).
TC7117 TC7117A
TYPICAL SEGMENT OUTPUT + V 0.5 mA TO SEGMENT 8 mA LATCH 7-SEGMENT DECODE 7-SEGMENT DECODE
7-SEGMENT DECODE
DIGITAL GROUND
THOUSANDS
HUNDREDS
TENS
UNITS
V+
TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK /4 CONTROL LOGIC 500
35 37
V+ TEST
21 40 OSC 1 39 OSC 2 38 OSC 3 1 HLDR ~70 k
DIGITAL GND
Figure 9. TC7117/TC7117A Digital Section 3-212
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TC7116 TC7116A TC7117 TC7117A
Reference Voltage
To generate full-scale output (2000 counts), the analog input requirement is VIN = 2 VREF. Thus, for the 200 mV and 2V scale, VREF should equal 100 mV and 1V, respectively. In many applications, where the ADC is connected to a transducer, a scale factor exists between the input voltage and the digital reading. For instance, in a measuring system the designer might like to have a full-scale reading when the voltage from the transducer is 700 mV. Instead of dividing the input down to 200 mV, the designer should use the input voltage directly and select VREF = 350 mV. Suitable values for integrating resistor and capacitor would be 120 k and 0.22 F. This makes the system slightly quieter and also avoids a divider network on the input. The TC7117/TC7117A, with 5V supplies, can accept input signals up to 4V. Another advantage of this system is when a digital reading of zero is desired for VIN 0. Temperature and weighing systems with a variable tare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between V+IN and analog common, and the variable (or fixed) offset voltage between analog com- mon and V IN.
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COMPONENT VALUE SELECTION Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on system noise. For 200 mV full scale, where noise is very important, a 0.47 F capacitor is recommended. On the 2V scale, a 0.047 F capacitor increases the speed of recovery from overload and is adequate for noise on this scale.
2 3 4 5 6 7
Reference Capacitor
A 0.1 F capacitor is acceptable in most applications. However, where a large common-mode voltage exists (i.e., - the VIN pin is not at analog common), and a 200-mV scale is used, a larger value is required to prevent roll-over error. Generally, 1 F will hold the roll-over error to 0.5 count in this instance.
Integrating Capacitor
The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not saturate the integrator swing (approximately 0.3V from either supply). In the TC7116/TC7116A or the TC7117/ TC7117A, when the analog common is used as a reference, a nominal 2V full- scale integrator swing is acceptable. For the TC7117/TC7117A, with 5V supplies and analog common tied to supply ground, a 3.5V to 4V swing is nominal. For 3 readings per second (48 kHz clock), nominal values for CINT are 0.22 1F and 0.10 F, respectively. If different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the output swing. The integrating capacitor must have low dielectric absorption to prevent roll-over errors. Polypropylene capacitors are recommended for this application.
TC7117/TC7117A POWER SUPPLIES
The TC7117/TC7117A are designed to operate from 5V supplies. However, if a negative supply is not available, it can be generated with a TC7660 DC-to-DC converter and two capacitors. Figure 10 shows this application. In selected applications, a negative supply is not required. The conditions for using a single +5V supply are: (1) The input signal can be referenced to the center of the common-mode range of the converter. (2) The signal is less than 1.5V. (3) An external reference is used.
+5V 35 36 V+ V+ REF LED DRIVE COM TC7117 TC7117A 8 2 + 10 F 4 TC7660 3+ 10 F 5 (-5V) GND V- 26 32 + V IN - TC04
Integrating Resistor
Both the buffer amplifier and the integrator have a class A output stage with 100 A of quiescent current. They can supply 20 A of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470 k is near optimum and, similarly, 47 k for 200 mV full scale.
+ V IN 31 - V IN 30 21
Oscillator Components
For all frequency ranges, a 100-k resistor is recommended; the capacitor is selected from the equation: f = 45 . RC For a 48 kHz clock (3 readings per second), C = 100 pF. TELCOM SEMICONDUCTOR, INC.
Figure 10. Negative Power Supply Generation With TC7660 3-213
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TC7116 TC7116A TC7117 TC7117A
TYPICAL APPLICATIONS
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
40 39 38 37 36 35 34 33 32 31 TC7116 TC7116A 30 29 28 27 26 25 24 23 22 21
SET VREF = 100 mV 100 k 100 pF 22 k 0.1 pF 1 k 1 M + IN + 47 k 0.22 F -
U/R
V+
40
TO LOGIC VCC
35
TO LOGIC GND
0.01 F 0.47 F -
TC7116 TC7116A
9V
O/R
26
V-
20
21
TO DISPLAY TO BACKPLANE
CD4023 OR 74C10 CD4077 O/R = OVERRANGE U/R = UNDERRANGE
Figure 11. TC7116/TC7116A Using the Internal Reference (200 mV Full Scale, 3 Readings Per Second (RPS)
Figure 13. Circuit for Developing Underrange and Overrange Signals from TC7116/TC7116A Outputs
40 39 38 37 36 35 34 33 32 31 TC7117 30 TC7117A 29 28 27 26 25 24 23 22 21
SET VREF = 100 mV
100 k 100 pF 22 k
40 39 38 37 36 35 34 33 32 31 TC7117 30 TC7117A 29 28 27 26 25 24 23 22 21
100 k 100 pF 10 k 0.1 pF 1 k
1.2V
SET VREF = 100 mV
+5V
0.1 pF 1 k 1 M
10 k
+ IN -
+ V TC9491CZM + IN -
0.01 F
0.47 F 47 k 0.22 F
0.01 F 0.47 F 47 k 0.22 F
1 M
-5V
V
-
TO DISPLAY
TO DISPLAY
Figure 12. TC7117/TC7117A Internal Reference (200 mV Full Scale, - 3 RPS, VIN Tied to GND for Single-Ended Inputs.)
Figure 14. TC7117/TC7117A With a 1.2V External Band-Gap - Reference (VIN Tied to Common)
3-214
TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
TC7116 TC7116A TC7117 TC7117A
1
TC7116 TC7116A TC7117 TC7117A
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
SET VREF = 1V 100 k 100 pF 24 k 0.1 F 25 k 1M + IN - 470 k 0.22 F V-
TC7117 TC7117A
V+
0.01 F 0.047 F
TO DISPLAY
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
2
100 k 100 pF 10 k 0.1 pF 1 k 1.2V 0.01 F 0.47 F 47 k 0.22 F 10 k + V TC9491CZM + IN - SET VREF = 100 mV
1 M
3 4 5 6 7
TO DISPLAY
Figure 15. Recommended Component Values for 2V Full Scale (TC7116/TC7116A and TC7117/TC7117A)
Figure 16. TC7117/TC7117A Operated from Single +5V Supply (An External Reference Must Be Used in This Application.)
APPLICATIONS INFORMATION
The TC7117/TC7117A sink the LED display current, causing heat to build up in the IC package. If the internal voltage reference is used, the changing chip temperature can cause the display to change reading. By reducing the LED common anode voltage, the TC7117/TC7117A package power dissipation is reduced. Figure 17 is a curve-tracer display showing the relationship between output current and output voltage for typical TC7117CPL/TC7117ACPL devices. Since a typical LED has 1.8V across it at 8 mA and its common anode is connected to +5V, the TC7117/TC7117A output is at 3.2V (Point A, Figure 17). Maximum power dissipation is 8.1 mA x 3.2V x 24 segments = 622 mW. However, notice that once the TC7117/TC7117A's output voltage is above 2V, the LED current is essentially constant as output voltage increases. Reducing the output voltage by 0.7V (Point B Figure 17) results in 7.7 mA of LED current, only a 5% reduction. Maximum power dissipation is now only 7.7 mA x 2.5V x 24 = 462 mW, a reduction of 26%. An output voltage reduction of 1V (Point C) reduces LED current by 10% (7.3 mA), but power dissipation by 38% (7.3 mA x 2.2V x 24 = 385 mW). Reduced power dissipation is very easy to obtain. Figure 18 shows two ways: Either a 5.1, 1/4W resistor, or a 1A diode placed in series with the display (but not in series with the TC7117/TC7117A). The resistor reduces the TC7117/TC7117A's output voltage (when all 24 segments are ON) to Point C of Figure 17. When segments turn off, the output voltage will increase. The diode, however, will result in a relatively steady output voltage, around Point B. In addition to limiting maximum power dissipation, the resistor reduces change in power dissipation as the display changes. The effect is caused by the fact that, as fewer segments are ON, each ON output drops more voltage and current. For the best case of six segments (a "111" display) to worst case (a "1888" display), the resistor circuit will change about 230 mW, while a circuit without the resistor will change about 470 mW. Therefore, the resistor will reduce the effect of display dissipation on reference voltage drift by about 50%. The change in LED brightness caused by the resistor is almost unnoticeable as more segments turn off. If display brightness remaining steady is very important to the designer, a diode may be used instead of the resistor.
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TELCOM SEMICONDUCTOR, INC.
3-215
TC7116 TC7116A TC7117 TC7117A
3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS WITH HOLD
+5V
+ 1 M TP3
IN -
-5V
24 k 1 k 100 pF TP5 100 k 40 TP2 TP1 35
150 k 0.47 F
0.01 F 0.1 F
0.22 F DISPLAY
47 k 30 TP 4
21
TC7117 TC7117A 1 10
20
DISPLAY 1.5, 1/4W 1N4001
Figure 17. TC7117/TC7117A Output Current vs Output Voltage
Figure 18. Diode or Resistor Limits Package Power Dissipation
3-216
TELCOM SEMICONDUCTOR, INC.

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